no of bit - variable

Hi,

Remember this is hardware and for a given bus the bits are fixed. If you mean how to use different indices per different instantiations or statements then you can use HDL to compute j,i and later use them provided they are integers.

example: fifo_data_in(191:0) written to 12 fifos and fifo_data_out(191:0) read out, each fifo is 16 bits wide)

g1: for i in 0 to 11 generate

TS_fifo: mpeg_fifo

port map(

aclr => reset,

data => fifo_data_in(i*16+15 downto i*16),

wrclk => rx_subclk,

wrreq => CA_vld_in(i),

rdclk => output_clk,

rdreq => read_fifo,

rdempty => fifo_empty(i),

rdfull => fifo_full(i),

wrusedw => fifo_wr_words(i),

q => fifo_data_out(i*16+15 downto i*16)

);

end generate;

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i am having the problem in verilog. i try to declare it as integer. However, there is a error state that it is not a constant.

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Hi,

I have forgotten verilog but can say that you shouldn't change the value of index(i,j) after the indexing statement. It should be ready before or inside the statement. Can you paste your relevant code sections here.

''what is k doing here? or in the other loop''

May be i should explain the background. The user can enter number of input and output in the range of 2 to 64 maximum. So the total number of input will be divided to 8 bits block by block. This is the function of k(8 loop maximum).

''this assignment has different widths ?''

The out_reg has 8 bits. however the number of bits assign to out_reg is depends on the formula.

for example

total number of input is 12 bits.

so, out_reg[0] has 8 bit(MSB)

then the remaining of 4 bits will be the LSB of out_reg[1](out_reg[1] has 8 bits too_