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Altera_Forum
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15 years ago

no failure or wainings reports for an obvious syntax error

i did not use the definition of register array ,reg [m-1:0] mem[n-1:0]; so when i assign them with original constant value with assign mem[0] = .....;then there were errors reports, and i modified the definition as :wire [m-1:0] mem[n-1:0]; i know that there is no this kind of definition at the verilog hdl syntax,but when i take a complete compilation,no error or warnings reports about this definition !so fancy,hope some helpful analysis,thks

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  • Altera_Forum's avatar
    Altera_Forum
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    Haoask07:

    only post a question once...

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    i did not use the definition of register array ,reg [m-1:0] mem[n-1:0]; so when i assign them with original constant value with assign mem[0] = .....;then there were errors reports, and i modified the definition as :wire [m-1:0] mem[n-1:0]; i know that there is no this kind of definition at the verilog hdl syntax,but when i take a complete compilation,no error or warnings reports about this definition !so fancy,hope some helpful analysis,thks

    --- Quote End ---