NO clock event, but signal changes anyway!

Wow, thanks for the VERY helpful insights / suggestions everyone. Excellent responses on this forum as usual.

Zooming in showed no glitch. You can advance to 'next transition' in my simulator (for any selected signal) and there is NO transition in this area that would drive a change in the process.

To solve the problem, as suggested, I now clock the latch using the system clock thus:

  proc_IOControlDBBusLatch : PROCESS (nRST, M4MHz)
  BEGIN
    IF nRST='0' THEN
      zb2D7_FrameBlank   <= '0';
      zb2D6_LineBlank    <= '0';
      zb2D5_CPU_Access   <= '0';
      zb2D4_AltGREENsel  <= '0';
      zb2D3_BANK3_CASsel <= '0';
      zb2D2_BANK2_CASsel <= '0';
      zb2D1_CassMotorEn  <= '0';
      zb2D0_SpeakerEn    <= '0';
    ELSIF RISING_EDGE(M4MHz) THEN
      IF nDB_BUF_EN='1' THEN
        --Latch data from the common databus
        zb2D7_FrameBlank   <= D_7_0(7);
        zb2D6_LineBlank    <= D_7_0(6);
        zb2D5_CPU_Access   <= D_7_0(5);
        zb2D4_AltGREENsel  <= D_7_0(4);
        zb2D3_BANK3_CASsel <= D_7_0(3);
        zb2D2_BANK2_CASsel <= D_7_0(2);
        zb2D1_CassMotorEn  <= D_7_0(1);
        zb2D0_SpeakerEn    <= D_7_0(0);
      END IF;
    END IF;
  END PROCESS proc_IOControlDBBusLatch;

The D_7_0(7 DOWNTO 0) signal(s) remains stable for the (total of 4) clocking pulses of M4MHz that is active for the above process when nDB_BUF_EN is at '1'.

I am now searching through the rest of my code for any other similar processes implemented in this manner.

Thanks again everyone!

Andy

PS,

For the record (in case any of you were wondering WHY I chose to use a logic source as a clocking event) these signals are driven from a Z80 core (actually a T80 core from opencores). Everything appears to 'do it's stuff' apart from a few issues (like this one) I am trying (very slowly) to hunt down.