NO clock event, but signal changes anyway!

From your description:

logic signals change that make nDB_BUF_EN='1'

logic signals change that STILL make nDB_BUF_EN='1'

To me, that's a glitch. I'm not good at simulation, but it's a hardware glitch. It's important to note that synthesis can change your logic too, which is another concern beyond what you're seeing. For example, I've seen synthesis take a signal that drives into a cloud of logic, and change it so that it drives multiple LUTs in that cloud. As a result, when that signal changes, a glitch occurs. For example, let's say your logic was an OR gate, and at least one signal was a constant high, so even if another signal is changing, the output should be stuck high. In reality it's that type of thing that is prone to glitching. You need to either take it off the clock and make it a clock enable as already suggested, or minimally re-register the logic so the final thing driving the clock signal is a register, which won't glitch assuming everything is synchronous. You may have other issues closing timing, but they'll be readily apparent in static timing analysis rather than glitches which are a pain to debug.

As for why it's not showing up in your simulation, I'm not sure. Don't simulators have a way to trace back what caused a signal to change, i.e. you can look at the register changing and ask the simulator to show what previous transition caused it? Again, I'm not a simulation person but thought that was possible. Maybe someone else can chime in. What simulator are you using?