NO clock event, but signal changes anyway!

@Kaz, nRST signal only goes from low to high right at the start of my simulation, so to answer your question, NO it is NOT changing at the point that the latched outputs change.

@Tricky, no nDB_BUF_EN is not a 'clock' per-se and yes it is derived logically. And yes I see one of the signals that nDB_BUF_EN is based on change and it is at this change that I see the latched outputs change.

BUT. But but but! I DO NOT see (in my simulation) nDB_BUF_EN change however the latched outputs DO change!

OK, you state "If it is logic from elsewhere being used as a clock you're in for trouble"... but why? Can a simulator 'not quite simulate' things correctly? Are you talking about some kind of logic race hazard here?

In other words (let me see if I can explain what I am thinking here)...

logic signals derive nDB_BUF_EN:

logic signals change that make nDB_BUF_EN='1'

logic signals change that STILL make nDB_BUF_EN='1', but somehow the simulator has decided that there was indeed a 'change' event in nDB_BUF_EN which therefore triggers my process above.

I have re-written the way in which nDB_BUF_EN is derived, and still I see this problem.

Thanks again chaps!

Andy