My SOPC has cfi_flash,and its base address is 0x0.But when I used the Flash Programmer in Nios IDE, it paused with No CFI table found at address 0x00000000 Leaving target processor paused It could't find the cfi_flash? I checked in Nios commend shell,also the problem. what's the matter?

Hi, I had the same problem in a design that has SOPC and a cfi flash. In my case, the problem was VHDL coding. The design worked fine in Quartus 5.1 but not in Quartus 7.1 Exact same code. We later found out that Quartus 6.X and later implemented stricter VHDL synthesis standards than Quartus 5.1. When we put a logic analyser on the pins, it looked the same for flash accesses, but the Flash Programmer in Nios IDE always gave the same error you described if the design was compiled using 7.1. I dont remember the exact coding that was the issue as I dont have the file diff's in front of me but I seem to remember that it had something to do with an inout port. The data was going out the FPGA ok but the input side was not getting to a lower level instantiation. It was the flash data pins that were not getting to where they needed to go, and with the flash reponding properly on the logic analyzer, it made debug really frustrating. Altera FAE informed us of the change in how quartus interpreted VHDL between 5.1 and 6.X and we made a simple fix to the code that allowed programming using 6.X and later versions of quartus. I'm not saying this is the problem you have but it was the issue I had with the same messages you are seeing.

You can try the memory test to see if your flash controller is working properly or not.

What type of Flash device is it and how is it connected to your system (in terms of SOPC components, address and data pins etc.)? It sounds like something pretty fundamental to me. Have you tried the --debug option with the flash programmer to see what other information you can glean?

Here is an example of the code problem I inherited. --- Quote Start --- entity example is port ( flash_data : inout std_logic_vector(7 downto 0)); end entity example; architecture rtl of example is signal flash_data_internal : std_logic_vector(7 downto 0); begin --this works in quartus 5.1 but not 6.0 and above flash_data <= flash_data_internal; flash_inst: entity work.flash(rtl) port map ( flash_data => flash_data_internal --flash_data is inout in flash.vhd ); --this is the proper way flash_inst: entity work.flash(rtl) port map ( flash_data => flash_data --direct to the input port. ); --- Quote End --- The flash_data_internal signal allows the data to go out but provides no path for the data coming in.

Thank you , Thank you , Thank you, Thank you. 4 days trying to debug this problem, 4 days, and your post saved my A**. It works now. Thank you again. Do you know why signals defined as inout wouldn't work with intermediate signals like this ? Edited to add this is for : gmpstr

No CFI table found at address 0x00000000 | Altera Community

19 Replies

Altera_Forum
Honored Contributor
12 years ago
I am getting error code 4 for nios-flash-programmer

Please find the attachment
output.txt18 KB
Altera_Forum
Honored Contributor
12 years ago
Hi

I tried like this

nios2-flash-programmer -g ro.flashs_ext_flash.flash --base=0x8000000
using cable "USB-Blaster [USB-0]", device 1, instance 0x00
Resetting and pausing target processor : OK
Checksum took 0.0z
erase not required
Program failed at offset 10001E
Leaving target processor paused

Error: Error code: 4 for command: nios2-flash-programmer "D:/web/webserver1/board_update_portal/software/web_server270813_bsp/flash/ro.flashfs_ext_flash.flash" --base=0x8000000 --sidp=0x8024E0 --id=0x0 --timestamp=1377500456 --device=1 --instance=0 '--cable=USB-Blaster on localhost [USB-0]' --program --verbose.
Altera_Forum
Honored Contributor
12 years ago
Are you sure of your base address ?

You have double extension on your flash file, maybe that cause problem

--- Quote Start ---
nios2-flash-programmer "D:/web/webserver1/board_update_portal/software/web_server270813_bsp/flash/ro.flashfs_ext_flash.flash"
--- Quote End ---

Maybe a watchdog

Maybe timing problems (mostly)

Regards
Altera_Forum
Honored Contributor
12 years ago
I am trying to execute example code only what ever i got from altera cyclone III development board examples

I installed the cyclone III fpga development kit

In that i have the board update portal.If i want to execute that file it is showing errors

In my cyclone III development board i am using S29GL512N flash
Altera_Forum
Honored Contributor
12 years ago
I ran into the same problem yesterday. I had a qsys system that was implemented and running, but I needed to add a Flash component for booting on power-up. After adding the Flash components in the System Contents view, I generated and compiled my design. Using the command line to program the device, I used these commands in a batch file:

nios2_command_shell.sh sof2flash --input=top_module.sof --output=flash_hw.flash --offset=0x20C0000 --pfl --optionbit=0x00030000 --programmingmode=PS
nios2_command_shell.sh nios2-flash-programmer --base=0x0 flash_hw.flash

The first command worked, but the programmer (2nd command) gave me the error ==> No CFI table found at address 0x00000000

I solved the problem because I realized I did not attached the data_master of the Nios to my avalon memory mapped slave port of the instanced External Flash. In fact, I only had the instruction master connected.

See the attached image for my solution. Hope this helps.
Altera_Forum
Honored Contributor
12 years ago
Hi all,
I've a similar problem due to a migration from SOPC design to Qsys, on Quartus 12.1 sp1.

Basically, it's a Nios2 linked to sram(32bit addr), f-ram(16bit addr.) and a flash cfi compliance (16bit addr.).
Now, I no longer able to download my firmware on cfi flash via nios2-flash-programmer ( No CFI table found at address... ).

In the Qsys design, I have one Generic Tri-State Controller for every memory device. They are connected to a Tri-State Conduit Pin Sharer and this is connected to Tri-State Conduit Bridge.

I'm able to read/write data from/to sram and fram and then I'm pretty sure the bus is ok.

Via oscilloscope, I checked that signals timings are ok. I noticed that, while in SOPC the flash memory access is @ 16bit, now in Qsys, the access is @ 32bit, but I don't thing this is the problem.

Any, ideas?

Thanks in advance,
Rino

p.s.
Sorry for my english
Altera_Forum
Honored Contributor
12 years ago
Hi, did you configure your CFI FLASH as a 16bit wide ?
It becomes hard to manually configure a CFI FLASH in QSYS (in version 12.0SP1). The documentation are incomplete, split. bad point from altera.
Altera_Forum
Honored Contributor
12 years ago
Hi,
yes. But I found the mistake even though I didn't completly understand the solution.

The flash is a 16bit data width, density 1Gbit then 26bit of addressing lines.
In the electrical scheme his address pin A00 is connected to the pin 01 of the address bus, A01 to pin02, A02 to pin 03 and so on.
Originally, I've done in this way:
--> in Qsys, when I instantiated the flash controller, I declared, in the generic tri-state controller, addr width = 26 and data width = 16.
Then I obtained an Out_addr : out std_logic_vector(25 downto 0).
--> On the top level, I wrote: Out_addr => PRIMARY_BUS_ADDR(26 down to 1), where PRIMARY_BUS_ADDR is a std_logic_vector(26 downto 0).
I thought it was ok, but I wasn't able to access to the flash memory.

After many tests, I declared:
--> in Qsys, in the generic tri-state controller, addr width = 27 , then I obtain an Out_addr : out std_logic_vector(26 downto 0)
--> on top level, Out_addr => PRIMARY_BUS_ADDR.

Now I can read/write the flash via nios2-flash-programmer and my system works fine...even though I didn't understand because in the first way it does not work.

Bye,
Rino
Altera_Forum
Honored Contributor
12 years ago
Nice you found.

There is a quite complex example in Altera Documentation of QSYS generic tri-stated components. --> http://www.altera.com/literature/hb/qts/qsys_system_components.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=qsys%20tri-state

I don't understand very well either.

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No CFI table found at address 0x00000000

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