Forum Discussion
Altera_Forum
Honored Contributor
12 years agoHi,
yes. But I found the mistake even though I didn't completly understand the solution. The flash is a 16bit data width, density 1Gbit then 26bit of addressing lines. In the electrical scheme his address pin A00 is connected to the pin 01 of the address bus, A01 to pin02, A02 to pin 03 and so on. Originally, I've done in this way: --> in Qsys, when I instantiated the flash controller, I declared, in the generic tri-state controller, addr width = 26 and data width = 16. Then I obtained an Out_addr : out std_logic_vector(25 downto 0). --> On the top level, I wrote: Out_addr => PRIMARY_BUS_ADDR(26 down to 1), where PRIMARY_BUS_ADDR is a std_logic_vector(26 downto 0). I thought it was ok, but I wasn't able to access to the flash memory. After many tests, I declared: --> in Qsys, in the generic tri-state controller, addr width = 27 , then I obtain an Out_addr : out std_logic_vector(26 downto 0) --> on top level, Out_addr => PRIMARY_BUS_ADDR. Now I can read/write the flash via nios2-flash-programmer and my system works fine...even though I didn't understand because in the first way it does not work. Bye, Rino