nios with ddr2 differential pin problem

I generated with QSYS a system with nios and ddr2.

This system is a component at vhd top-level.

I run the pin assignment tcl that made for the ddr2.

I named the out-pins from the top level same as the QSYS Instantiation.

The DDR2 is connected directly out of the design.

When it starts to place and route its give me error.

"Error: Can't place differential I/O positive pin at a differential I/O negative location."

This error is for the "memory_mem_ck" and "memory_mem_ck_n" signal generated by QSYS.

I tried to swich them but with no success.

How can I fix this? add something in the QSF file? some constrains?

The device is Stratix III.

Thank you and sorry for my bad English.