Honored Contributor
Honored Contributorhi,
thanks for the reply... i downloaded some development kit version v9.0 from their ftp link ... But I have one question ..whenever i try to build system from scratch, i have problems getting the same settings as in the standard for the Altera Memory Controller for DDR2 SDRAM... specifically among the last 6 settings, some entries are set to 0.0 in the standard design.,...when I try to enter it, it sees valid values are only between 1.2 to 6... something like that ... Even if build the system with this settings...then i cannot download the program ..because debug cable gives an error "m_state == debug " failed and this is because of timing errors in DDR2 controller... do u know how to get the system up from scratch using DDR2 MemPhy controller.. pramod
