Nios SRAM interface

Answering my own query, it would appear that the IDT71V416 interface provided assumes that there are two SRAM parts on the board not one. The answer appears to be to create a new Avalon tri-state slave and hook that up to the tri-state bridge and that works.

I have one residual query - in order to get the SOPC to recognise that the new slave is a memory device, you have to set the apparently deprecated option "Memory device" - what is the revised mechanism?

Lomax

I am a new beginner of SOPC. I am facing the same problem as you. Can you further explain on how u solve?.. I using the method u said above but i still get the error==>

Error: The node "nios_ii:nios0|tristate_bridge_ssram_avalon_slave_arbitrator:the_tristate_bridge_ssram_avalon_slave|incoming_data_to_and_from_the_ssram[27]" has multiple drivers due to the always-enabled I/O buffer "nios_ii:nios0|data_to_and_from_the_ssram[27].

What I should do for the be_n, LB and UB?

The Avalon Memory Mapped Tristate Slave has all the signals that you need for that chip. The resulting TCL file looks like this :

package require -exact sopc 9.1# | # +-----------------------------------# +-----------------------------------# | module memtest# |

set_module_property NAME memtest

set_module_property VERSION 1.0

set_module_property INTERNAL false

set_module_property GROUP Interfaces

set_module_property DISPLAY_NAME memtest

set_module_property TOP_LEVEL_HDL_FILE memtest.v

set_module_property TOP_LEVEL_HDL_MODULE memtest

set_module_property INSTANTIATE_IN_SYSTEM_MODULE true

set_module_property EDITABLE true

set_module_property ANALYZE_HDL AUTO# | # +-----------------------------------# +-----------------------------------# | files# |

add_file memtest.v {SYNTHESIS SIMULATION}# | # +-----------------------------------# +-----------------------------------# | parameters# | # | # +-----------------------------------# +-----------------------------------# | display items# | # | # +-----------------------------------# +-----------------------------------# | connection point s0# |

add_interface s0 avalon_tristate end

set_interface_property s0 activeCSThroughReadLatency false

set_interface_property s0 explicitAddressSpan 0

set_interface_property s0 holdTime 0

set_interface_property s0 isMemoryDevice true

set_interface_property s0 isNonVolatileStorage false

set_interface_property s0 maximumPendingReadTransactions 0

set_interface_property s0 printableDevice false

set_interface_property s0 readLatency 0

set_interface_property s0 readWaitStates 0

set_interface_property s0 readWaitTime 0

set_interface_property s0 setupTime 0

set_interface_property s0 timingUnits Cycles

set_interface_property s0 writeWaitTime 0

set_interface_property s0 ASSOCIATED_CLOCK clock_reset

set_interface_property s0 ENABLED true

add_interface_port s0 ats_s0_address address Input 18

add_interface_port s0 ats_s0_rd_n read_n Input 1

add_interface_port s0 ats_s0_data data Bidir 16

add_interface_port s0 ats_s0_we_n write_n Input 1

add_interface_port s0 ats_s0_ce_n chipselect_n Input 1

add_interface_port s0 ats_s0_be_n byteenable_n Input 2# | # +-----------------------------------# +-----------------------------------# | connection point SRAM# |

add_interface SRAM conduit end

set_interface_property SRAM ENABLED true

add_interface_port SRAM SRAM_ADDR export Output 18

add_interface_port SRAM SRAM_RD_N export Output 1

add_interface_port SRAM SRAM_WE_N export Output 1

add_interface_port SRAM SRAM_BE_N export Output 2

add_interface_port SRAM SRAM_CE_N export Output 1# | # +-----------------------------------# +-----------------------------------# | connection point clock_reset# |

add_interface clock_reset clock end

set_interface_property clock_reset ENABLED true

add_interface_port clock_reset clk clk Input 1

add_interface_port clock_reset reset reset Input 1# | # +-----------------------------------

I think that effectively creates a conduit for you to access all the relevant signals at the level above which then has the following :

output [17:0] SRAM_ADDR;

inout [15:0] SRAM_DQ;

output SRAM_WE_N;

output SRAM_OE_N;

output SRAM_UB_N;

output SRAM_LB_N;

output SRAM_CE_N;

wire [17:0] SRAM_ADDR;

wire SRAM_UB_N;

wire SRAM_LB_N;

wire [15:0] SRAM_DQ;

wire SRAM_OE_N;

wire SRAM_WE_N;

wire SRAM_CE_N;

nios_system NiosII (

.clk_0 (CLOCK_50),

.reset_n (KEY[0]),

.sram_s0_data (SRAM_DQ),

.SRAM_ADDR_from_the_sram (SRAM_ADDR),

.SRAM_BE_N_from_the_sram ({SRAM_UB_N, SRAM_LB_N}),

.SRAM_CE_N_from_the_sram (SRAM_CE_N),

.SRAM_RD_N_from_the_sram (SRAM_OE_N),

.SRAM_WE_N_from_the_sram (SRAM_WE_N),

);

Hope this helps.

Lomax