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Altera_Forum's avatar
Altera_Forum
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17 years ago

Newbie to Quartus II, Can't find ram.vhd refered to in Tutorial

Hi,

I'm a newbie to Quartus II.

I've just downloaded and installed the Quartus II 8.0 sp1 Web Edition software which I'm running under Vista Ultimate on my notebook. I've been going through the tutorial and have gotten to Module 2:Create a Design, Step 1: Create a new Project in which it says at page 2 of the New Project Wizard

"In the add files page, we browse to the default working directory to locate the ram.vhd file".

I've searched both drives of my notebook and have been unable to locate this file, nor was there a default working directory C:\quartus\tutorial as shown in the tutorial.

I've also downloaded theThe Quartus II Software Interactive Tutorial Zip file and have searched for ram.vhd on the Altera website but have not found the file in either. Can anyone help with the location of the file, or does it not come with the web edition of Quartus II maybe?

I had previously run the "How to begin a simple FPGA design" tutorial and found that the simple_counter.v file was part of the CIII_Starter_Kit-v7.2.0 documentation which I had to download and install separately. Is it possible that the ram.vhd file is part of another starter kit?

Oh and just in case anyone mentions it, I was not shouting by putting Add Files and ram.vhd in bold type. That's how it appears in the tutorial.

Many thanks in advance.

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    Step 1 of tutorial 1 is broken, that seemed to me to be beyond unprofessional.

    Now I learn this has been a known issue for FOUR YEARS?!

    Should I be worried that this company has just stopped trying?

    --- Quote End ---

    DEAR PEOPLE FROM THE FUTURE: Here's what we've figured out so far ...

    The bad news is that the "Getting Started Tutorial" found in Quartus is not intended to be something you actually follow along with at home, and has remained this way for many years. It just introduces you to the GUI elements and some of the process flow. Arguably, if you need to be walked through a GUI by the hand with "click here, then click there" video and then quizzed on the subject afterwards, you should ask yourself whether FPGA development is really for you.

    The good news is that Altera has a pretty good tutorial called "My First FPGA" found in http://www.altera.com/literature/tt/tt_my_first_fpga.pdf that really is something you can follow along with at home. Other tutorials can be found via the Altera literature index, or in the quartus\common\help folder as PDF files.

    I know that this threat has been dormant for a while, but hopefully this answer clears things up a little as the issue is still present as of v13.1.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    I downloaded an Altera Quartus Version 13.0 SP1 after purchasing a Cyclone II Development Board, which I have great enthusiasm for learning FPGA Programming. I am going through the tutorial and encountered the same issues as others have posted here years earlier - and to no resolution from Altera.

    I have to say that I am greatly disappointed that Altera would release a tutorial that is incomplete at best, broken which is more realistic to most reading this. The purpose of a tutorial is to walk us through the process of how to create a simple project; not to leave us stranded on a broken road to nowhere.

    For the amount of money I paid for my development board, I should expect tutorials to be in working order and complete if Altera would like to keep their customers happy and to improve their FPGA skills. Xilinx is another FPGA manufacturer. Is the message from Altera to tell us new customers that they want us to move on to another manufactuerer?
  • Ed1632's avatar
    Ed1632
    Icon for New Contributor rankNew Contributor
    1 year ago

    Hi all, quick update. I am working on The Intel Quartus Prime: Foundation (Standard Edition) Online Tutorial, as recommended in the Beginner Altera FPGA Designer learning plan. There were no example files included in the tutorial, just 3 PDF's and a 15_1_V1 installer (I am working on 23.1). The tutorial slides are dated 2015.

    I found pipemult.vhd on GitHub, I can't speak for it's veracity, but it does appear to get through Analysis and Elaboration (with the changes specified in the lab instructions).

    I think this tutorial still has useful sections, but much of it is outdated, and the labs are incomplete as others have mentioned.

    --*****************************************************************************
    -- *
    -- Copyright (C) 2009 Altera Corporation *
    -- *
    -- ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX *
    -- are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. *
    -- *
    -- All information provided herein is provided on an "as is" basis, *
    -- without warranty of any kind. *
    -- *
    -- Module Name: pipemult File Name: pipemult.vhd *
    -- *
    -- Module Function: This file contains the top level module for the pipemult *
    -- project. *
    -- *
    -- REVISION HISTORY: *
    -- Revision 1.0 12/07/2009 - Initial release *
    --*****************************************************************************

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;

    LIBRARY work;

    ENTITY pipemult IS
    port (
    clk1 : IN STD_LOGIC;
    wren : IN STD_LOGIC;
    dataa : IN STD_LOGIC_VECTOR( 7 downto 0);
    datab : IN STD_LOGIC_VECTOR( 7 downto 0);
    rdaddress : in STD_LOGIC_VECTOR( 4 downto 0);
    wraddress : IN STD_LOGIC_VECTOR( 4 downto 0);
    q : OUT STD_LOGIC_VECTOR(15 downto 0)
    );
    END pipemult;

    ARCHITECTURE bdf_type OF pipemult IS

    -- Insert multiplier component declaration here

    component ram
    PORT (
    clock : in STD_LOGIC;
    data : in STD_LOGIC_VECTOR (15 DOWNTO 0);
    rdaddress : in STD_LOGIC_VECTOR (4 DOWNTO 0);
    wraddress : in STD_LOGIC_VECTOR (4 DOWNTO 0);
    wren : IN STD_LOGIC := '1';
    q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
    );
    end component;

    signal mult_to_ram, ram_out : STD_LOGIC_VECTOR(15 downto 0);


    BEGIN


    -- Insert multipler instantiation here


    ram_inst : ram
    PORT MAP(clock => clk1,
    wren => wren,
    data => mult_to_ram,
    rdaddress => rdaddress,
    wraddress => wraddress,
    q => ram_out);

    out_proc : PROCESS (clk1)
    BEGIN
    IF rising_edge (clk1) THEN
    q <= ram_out;
    END IF;
    END PROCESS out_proc;

    END;