Newbie to Quartus II, Can't find ram.vhd refered to in Tutorial

Hi all, quick update. I am working on The Intel Quartus Prime: Foundation (Standard Edition) Online Tutorial, as recommended in the Beginner Altera FPGA Designer learning plan. There were no example files included in the tutorial, just 3 PDF's and a 15_1_V1 installer (I am working on 23.1). The tutorial slides are dated 2015.

I found pipemult.vhd on GitHub, I can't speak for it's veracity, but it does appear to get through Analysis and Elaboration (with the changes specified in the lab instructions).

I think this tutorial still has useful sections, but much of it is outdated, and the labs are incomplete as others have mentioned.

--*****************************************************************************
-- *
-- Copyright (C) 2009 Altera Corporation *
-- *
-- ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX *
-- are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. *
-- *
-- All information provided herein is provided on an "as is" basis, *
-- without warranty of any kind. *
-- *
-- Module Name: pipemult File Name: pipemult.vhd *
-- *
-- Module Function: This file contains the top level module for the pipemult *
-- project. *
-- *
-- REVISION HISTORY: *
-- Revision 1.0 12/07/2009 - Initial release *
--*****************************************************************************

LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY work;

ENTITY pipemult IS
port (
clk1 : IN STD_LOGIC;
wren : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR( 7 downto 0);
datab : IN STD_LOGIC_VECTOR( 7 downto 0);
rdaddress : in STD_LOGIC_VECTOR( 4 downto 0);
wraddress : IN STD_LOGIC_VECTOR( 4 downto 0);
q : OUT STD_LOGIC_VECTOR(15 downto 0)
);
END pipemult;

ARCHITECTURE bdf_type OF pipemult IS

-- Insert multiplier component declaration here

component ram
PORT (
clock : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (15 DOWNTO 0);
rdaddress : in STD_LOGIC_VECTOR (4 DOWNTO 0);
wraddress : in STD_LOGIC_VECTOR (4 DOWNTO 0);
wren : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component;

signal mult_to_ram, ram_out : STD_LOGIC_VECTOR(15 downto 0);

BEGIN

-- Insert multipler instantiation here

ram_inst : ram
PORT MAP(clock => clk1,
wren => wren,
data => mult_to_ram,
rdaddress => rdaddress,
wraddress => wraddress,
q => ram_out);

out_proc : PROCESS (clk1)
BEGIN
IF rising_edge (clk1) THEN
q <= ram_out;
END IF;
END PROCESS out_proc;

END;