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Altera_Forum's avatar
Altera_Forum
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17 years ago

Newbie Question

Hi guys. I am new at VHDL and Quartus II software so this might be a really stupid or trivial question but I can't seem to figure out why the following code is giving a syntax error "near text "PROCE...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

The compiler is complaining about missing end if statements. That's because the correct syntax is 

IF <cond1> THEN
  <block1>
ELSIF <cond2> THEN
  <block2>
ELSE
  <block3>
END IF;

Quartus has nice VHDL templates accessible in the editor, they can help you in case of VHDL syntax doubts.