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Altera_Forum's avatar
Altera_Forum
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13 years ago

Newbie Parameter Q

Could someone tell me if I am misusing Quartus/SOPC Builder or if this is an actual compiler bug (I'm betting on# 1).......

I have 4 parameters in a Verilog file...

parameter P1 = 0;

parameter P2 = 1;

parameter P3 = 2;

parameter P4 = 3;

When I edit in Component Builder, no errors

If I insert the component into my SOPC design and compile, no errors

If I compile in Quartus no errors.

Am using these the parameters as states to a state machine. Kept getting to state P3 and staying there. After some exploration, it turns out that the Verilog file created when I added the module to SOPC defined them as:

parameter P1 = 0;

parameter P2 = 1;

parameter P3 = 2;

parameter P4 = 2; ????????

If I change the name P4 and the value, it will update the first time (e.g., parameter P5 = 8). However, further changes to P5 are not reflected into the instantiation V file.

Any help is appreciated,

ME

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    BTW, if I open it in component editor, and look at the HDL parameters tab, it displays the "incorrect" value?

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Look in your _hw.tcl file. That is where the default values for the parameters are defined.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Thanks Dave,

    Agreed...What I'm curious about is if I change a value in my "source", why doesn't it get updated in the tcl file?

    ME
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    When I edit the component, save it and regenerate the SOPC Builder file?

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Trace your parameters and you'll see why.

    In SOPC Builder or Qsys, you'll have a component instance, lets call it, mycomponent_0.v, which is an instance of your mycomponent.v.

    Inside mycomponent_0.v there are overrides for the generics on your mycomponent.v.

    If you are using parameters solely to implement state machine states, and you do not want to be able to edit those parameters from your _hw.tcl file, then just replace them in mycomponent.v with localparam and they'll be local to your mycomponent.v file.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hey Dave,

    Many Thanks...! That fixed my problem.

    Now a silly Q. Why the differentiation. I read up on parameter and localparam and understand HOW the language is implemented. I guess my question is WHY? If I create a module with parameters with explicit values, why would the instantiation choose a "default" set?

    Thanks much for all of your guidance....

    ME
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    Many Thanks...! That fixed my problem.

    --- Quote End ---

    Great!

    --- Quote Start ---

    Now a silly Q. Why the differentiation.

    --- Quote End ---

    One is local, its there to make the code easier to read. The parameter or generics are there to generalize the component.

    --- Quote Start ---

    If I create a module with parameters with explicit values, why would the instantiation choose a "default" set?

    --- Quote End ---

    Parameters must always be defined. In VHDL, the component definition can have defaults for the unused generics.

    In your case, there is no 'default' set. The parameters are always setup by the _hw.tcl file. So in this case, Quartus via Qsys or SOPC Builder is just instantiating the component with the parameters indicated by the _hw.tcl file (unless those values are over-ridden by user in the Qsys/SOPC configuration GUI). Since you probably didn't want the state machine states to be overridden by the user, the state machine states should never have been parameters in the first place.

    Fundamentally, this is a problem with you using Verilog. I suspect you wrote your state machine using parameters, as that is what you saw in an example. However, there's lots of bad examples of Verilog, and you picked one of them. Verilog had poor support for advanced programming features, eg., it did not have enumerations, so you'll find state machine examples where the states are created with 'define or parameter.

    Verilog is now a subset of the SystemVerilog language. SystemVerilog has enumerations and better environments for describing synchronous (always_ff) and combinatorial (always_comb) logic. Take the time to learn SystemVerilog and start using its features. Its pretty well supported in Quartus now.

    Cheers,

    Dave