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Many Thanks...! That fixed my problem.
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Great!
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Now a silly Q. Why the differentiation.
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One is local, its there to make the code easier to read. The parameter or generics are there to generalize the component.
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If I create a module with parameters with explicit values, why would the instantiation choose a "default" set?
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Parameters must always be defined. In VHDL, the component definition can have defaults for the unused generics.
In your case, there is no 'default' set. The parameters are always setup by the _hw.tcl file. So in this case, Quartus via Qsys or SOPC Builder is just instantiating the component with the parameters indicated by the _hw.tcl file (unless those values are over-ridden by user in the Qsys/SOPC configuration GUI). Since you probably didn't want the state machine states to be overridden by the user, the state machine states should never have been parameters in the first place.
Fundamentally, this is a problem with you using Verilog. I suspect you wrote your state machine using parameters, as that is what you saw in an example. However, there's lots of bad examples of Verilog, and you picked one of them. Verilog had poor support for advanced programming features, eg., it did not have enumerations, so you'll find state machine examples where the states are created with 'define or parameter.
Verilog is now a subset of the SystemVerilog language. SystemVerilog has enumerations and better environments for describing synchronous (always_ff) and combinatorial (always_comb) logic. Take the time to learn SystemVerilog and start using its features. Its pretty well supported in Quartus now.
Cheers,
Dave
Honored Contributor
