New to VHDL. Help with errors

Can you tell me why im getting these errors for this code:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_unsigned.all;

ENTITY DAC2 IS

PORT( hardwarecontrol: IN STD_LOGIC; -- Control Hardware Shut Down

input: IN STD_LOGIC_VECTOR (11 DOWNTO 0); -- Input Value for sine wave

clock: IN STD_LOGIC; -- Clock Input from Altera Board

cs: OUT STD_LOGIC; -- Chip Select

sck: OUT STD_LOGIC; -- Serial Clock Input

sdi: OUT STD_LOGIC; -- Serial Data Input

ldac: OUT STD_LOGIC; -- Latch DAC Input

shdn: OUT STD_LOGIC -- Hardware Shutdown Input

);

END DAC2;

ARCHITECTURE behaviour OF DAC2 IS

SIGNAL count: STD_LOGIC_VECTOR (3 DOWNTO 0);

BEGIN

sck <= clock;

IF RISING_EDGE(clock) THEN

IF (hardwarecontrol = '1') THEN

cs <= '0';

ldac <= '1';

PROCESS(clock,input)

BEGIN

IF (count = "0000") THEN

sdi <= '0';

ELSIF (count = "0001") THEN

sdi <= '1';

ELSIF (count = "0010") THEN

sdi <= '0';

ELSIF (count = "0011") THEN

sdi <= '1';

ELSIF (count = "0100") THEN

sdi <= input(11);

ELSIF (count = "0101") THEN

sdi <= input(10);

ELSIF (count = "0110") THEN

sdi <= input(9);

ELSIF (count = "0111") THEN

sdi <= input(8);

ELSIF (count = "1000") THEN

sdi <= input(7);

ELSIF (count = "1001") THEN

sdi <= input(6);

ELSIF (count = "1010") THEN

sdi <= input(5);

ELSIF (count = "1011") THEN

sdi <= input(4);

ELSIF (count = "1100") THEN

sdi <= input(3);

ELSIF (count = "1101") THEN

sdi <= input(2);

ELSIF (count = "1110") THEN

sdi <= input(1);

ELSIF (count = "1111") THEN

sdi <= input(0);

cs <= '1';

ldac <= '0';

shdn <= '1';

END IF;

count <= count +1;

END PROCESS;

ELSIF (hardwarecontrol = '0') THEN

count <= "0000";

END IF;

END IF;

END behaviour;

Error (10500): VHDL syntax error at DAC2.vhd(26) near text "IF"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement

Error (10500): VHDL syntax error at DAC2.vhd(26) near text "THEN"; expecting "(", or "'", or "."

Error (10500): VHDL syntax error at DAC2.vhd(27) near text "THEN"; expecting "<="

Error (10500): VHDL syntax error at DAC2.vhd(85) near text "ELSIF"; expecting "end", or "(", or an identifier ("elsif" is a reserved keyword), or a concurrent statement

Error (10500): VHDL syntax error at DAC2.vhd(85) near text "THEN"; expecting "<="

Error (10500): VHDL syntax error at DAC2.vhd(87) near text "IF"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture