New to VHDL. Help with errors

hello everyone...

can anyone tell me whats wrong wif diz code?

component RAM is

generic (K, W: integer); -- number of address and data bits

port (WR: in std_logic); -- active high write enable

ADDR : in std_logic_vector (W-1 downto 0); -- RAM address

DIN: in std_logic_vector (K-1 downto 0); -- write data

DOUT: out std_logic_vector (K-1 downto 0); -- read data

end component RAM;

i new with vhdl, i now working my final year project using vhld, so i in learning process.

this code give me error 10500

"Error (10500): VHDL syntax error at fifo.vhd(25) near text "ADDR"; expecting "end""

TQVM in advance...