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There is nothing wrong with this for altera chips, as long as key is synchronised. There are no sync resets on altera registers, only async ones. Sync resets have to be emulated with a mux. So using an async reset from a synchronous source is actually the best way to reset registers because you use the least logic.
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Yeah Tricky, I have accept that. but the concern is deftonesrc reset the clock_1k signal in two process. One is with respect to reset signal in one process, and with respect to KEY(0) signal. So I just combined both logics in one process. Otherwise I dont have any concern about async reset.
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