New to VHDL. . . and this error is adding years to my life!

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Hi, In your Clock_Gen_100Hz process you have used KEY(0) as asyn reset.Instead of that give high priority to reset and within clcok give priority to key(0).

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There is nothing wrong with this for altera chips, as long as key is synchronised. There are no sync resets on altera registers, only async ones. Sync resets have to be emulated with a mux. So using an async reset from a synchronous source is actually the best way to reset registers because you use the least logic.