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Altera_Forum's avatar
Altera_Forum
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13 years ago

New to VHDL. . . and this error is adding years to my life!

Hello all. New to this forum, and will probably be more active since this stuff is not innate to me. Anyways, I am trying to make a stopwatch that has the following properties: 1. When you pres...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hi, In your Clock_Gen_100Hz process you have used KEY(0) as asyn reset.Instead of that give high priority to reset and within clcok give priority to key(0).I have modified as

IF(reset='1') THEN --KEY0 is the asynchronous reset button

clock_1k <= '0';

loopcount := 0;

ELSIF(clock_50'event AND clock_50 = '1') THEN

IF(KEY(0) = '0') THEN

clock_1k <= '0';

loopcount := 0;

elsif(loopcount = 2499999) then

loopcount := 0;

clock_1k <= not clock_1k; --flip clock_10K

else

loopcount := loopcount + 1;

end if;

END IF;

And Dont forget remove assignment of clock_1k <= '0'; from FSM process.