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Altera_Forum's avatar
Altera_Forum
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13 years ago

New to VHDL. . . and this error is adding years to my life!

Hello all. New to this forum, and will probably be more active since this stuff is not innate to me. Anyways, I am trying to make a stopwatch that has the following properties: 1. When you pres...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

OK, I see what you are saying. Then I am unsure how I am to get the counter to "reset" during the FSM state "pause". I think the problem is that I am not really defining the function of "reset", and I dont quite see how to do this without making 2 processes be able to set the counter generated from clock1k to '0'

EDIT: Nevermind, I just figured it out! Thank you so much for your help!