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Altera_Forum's avatar
Altera_Forum
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13 years ago

New to VHDL. . . and this error is adding years to my life!

Hello all. New to this forum, and will probably be more active since this stuff is not innate to me. Anyways, I am trying to make a stopwatch that has the following properties: 1. When you pres...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

You are assigning a value to clock_1k in more than one process.

FSM: Process(clock_1k, buttonpress, reset)

Clock_Gen_100Hz: PROCESS (clock_50, KEY(0))

These two processes both modify the clock_1k signal. That is incorrect behavior. Get rid of it in the FSM process and the error will go away.