Honored Contributor
Honored ContributorHiya, I am struggling with this a little.
even putting a register before my outputs doesn't seem to work, as the 3ns delay appears to be across the tristate buffer for the IO pin. As I need the pin to be an IO pin is there another way to make it meet the 11ns setup time requirement? or do I need to look into multicycling and rather than having my latch clock on the next rising edge of the latch clock, have it on the rising edge after that? with registers, here is my timing, and the locations of the paths within the RTL viewer. I don't really know how FTDI expect you to be able to meet the 11ns setup with a clock period of 16.67ns and the typical data and clock delays that I am recieving!? Reagrds, Lee H
