New to quartus, please help

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... after Compiling code/schematic, the tutorial says I can view equations in the Report, under Analysis and Synthesis but there is no Equations tab there of any kind.

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To generate equations files when you compile, enable Tools --> Options --> General --> Processing --> Automatically generate equation files during compilation. The Analysis & Synthesis and Fitter compilation reports will have a section referring to these separate files.

To generate equations files only when you need them, run Processing --> Start --> Start Equation Writer.

Regardless of whether you generate the equations files during compilation or on demand after compilation, I recommend enabling Tools --> Options --> General --> Processing --> Automatically generate HTML-Format Report Files (.htm) after design processing. The hyperlinks make it easy to trace backward through the equations.

There are places to see equations in the GUI even if you do not generate equations files. Open Assignments --> Timing Closure Floorplan or Tools --> Chip Planner, whichever one your device family supports. (In Quartus II version 7.1, most device families support both.) With the new window as the active window, enable View --> Equations. A pane at the bottom of the Timing Closure Floorplan or Chip Planner window will show the equations for whatever is currently selected. If you don't see the equations pane, look for a horizontal separator that you need to drag up. From most places in Quartus where Locate is on the right-click menu, you can locate a node to these windows to select the node automatically so that you don't have to search for it.

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I'm not sure how to get it to become represented by NAND gates.

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You might have been taught how all Boolean logic can be reduced to a set of NAND gates. ASIC gate arrays actually implement logic as low-level gates. But a CPLD or FPGA does not.

A CPLD like a MAX (not MAX II) device implements logic in sum-of-products form. It ANDs things together and then ORs together the product terms. It might also have built-in XOR gates and inverters. These logic resources optionally feed registers. If your entire design were a single NAND gate, it would get transformed into a logical form that maps directly to these device logic resources.

An FPGA has LUTs and registers. All the Boolean logic gets transformed into something that can be mapped into look-up tables (4-input LUTs for most device families, larger LUTs for some families). If your entire design were a single 2-input NAND gate, it would be implemented as a little ROM that has two inputs of the LUT used. The memory contents of the ROM produce the NAND result on the output for all input signal combinations.

You should write your VHDL or Verilog HDL in an RTL form that follows the recommended coding guidelines (see http://www.alteraforum.com/forum/showthread.php?t=1024) and that is easy to understand and maintain. Let the synthesis tool take care of how the logic maps into these hardware resources.

Is it a Quartus lab, or are you trying to use Quartus to verify your work for a lab that does not require compiling for a CPLD or FPGA? As I said, Quartus is not going to do a NAND implementation like an ASIC gate array would.

If you want to verify that your NAND-only adder has the correct functionality, you can come closer to just NANDs in Quartus by inserting an LCELL primitive after each NAND (or maybe by using a "keep" attribute in the HDL file). You will get one NAND function per CPLD macrocell or FPGA LUT, but each logic cell or LUT will still be what I described before for a design that is a single NAND gate. There are other posts on this forum that discuss using LCELL primitives.