New to quartus, please help

Is it a Quartus lab, or are you trying to use Quartus to verify your work for a lab that does not require compiling for a CPLD or FPGA? As I said, Quartus is not going to do a NAND implementation like an ASIC gate array would.

If you want to verify that your NAND-only adder has the correct functionality, you can come closer to just NANDs in Quartus by inserting an LCELL primitive after each NAND (or maybe by using a "keep" attribute in the HDL file). You will get one NAND function per CPLD macrocell or FPGA LUT, but each logic cell or LUT will still be what I described before for a design that is a single NAND gate. There are other posts on this forum that discuss using LCELL primitives.