New Quartus versions is reason for timing constraints fails

Yes, I can Confirm. With this additional assignment - timing are met with with minimum hold slack 0.402 and setup slack 0.082.

What is the kind of magic? Can you give advice, where and how you know what numbers should be?

Same time, i go another way. I've noticed timequest warning

Warning (176441): The I/O pin RX_DATA[7] cannot meet the timing constraints due to conflicting requirements. The I/O pin is a PLL compensated I/O, but the setup/hold requirements are in conflict with the source PLL mode(source synchronous or ZDB).
Info (176440): Auto delay chain can't change the delay chain setting on I/O pin RX_DATA[6] since it's a PLL compensated pin
Info (176440): Auto delay chain can't change the delay chain setting on I/O pin RX_DATA[5] since it's a PLL compensated pin
Info (176440): Auto delay chain can't change the delay chain setting on I/O pin RX_DATA[4] since it's a PLL compensated pin
Info (176440): Auto delay chain can't change the delay chain setting on I/O pin RX_DATA[3] since it's a PLL compensated pin
Info (176440): Auto delay chain can't change the delay chain setting on I/O pin RX_DATA[2] since it's a PLL compensated pin
Info (176440): Auto delay chain can't change the delay chain setting on I/O pin RX_DATA[1] since it's a PLL compensated pin
Warning (176441): The I/O pin RX_DATA[0] cannot meet the timing constraints due to conflicting requirements. The I/O pin is a PLL compensated I/O, but the setup/hold requirements are in conflict with the source PLL mode(source synchronous or ZDB).

and PLL add huge delay.

Without pll, timings are met..

Then i use LVDS_RX with deser=4 instead of ALTDDIO_IN and just drop 2/4 samples, fitter place input paths in another "faster" location and timing are met too!

Thanks in advance for helping dig deeper in timing constraints and analyse!