Neuron implementation in VHDL (code attached)

Any signal (a port is also a signal) that has an effect on any other signal inside the process must be in the sensitivity list for the simulation to match the real hardware behaviour. Synthesis ignores sensitivity lists.

So anything inside an If, elseif, case statement or on the right hand side of an assignment must be in the sensitivity list., Unless it is a synchronous process, when only the clock and any asynchronous reset signals need to be in there.

Processes are never "called" they execute forever, from time 0 to the end of simulation. They will be re-evaluated every time a signal in the sensitivity list changes.