Neighboring PLLs

Chaining PLLs is quite normal to my opinion as a means of clock distribution with Cyclone III and other FPGAs that allow it. But depending on the intended clock network structure, driving PLLs from remote clock pins may be meaningful as well. Quartus will find reasons to complain in both cases...

Regarding the Timequest errors: If they are concerning the relation of different clock domains (e. g. DDR controller to loacal bus), you probably didn't contrain the clock domains sufficient. The PLLs should be able to achieve any intended relation of clock domains. If they are internal to DDR PLL clock domain, they shouldn't depend on how the PLL is clocked.