Neighboring PLLs

Does chaining the PLLs for this configuration make sense? I wasn't quite sure how to handle feeding 2 separate PLLs from a single clock source on the starter board. There's no real motivation for chaining them in terms of needs to achieve a really high multiplier / divisor that wouldn't otherwise be possible with a single stage.

If I set it up both PLLs to be fed from the "osc_clk" V9 pin on the board, then whichever one doesn't get mapped to PLL#4 gets a single warning saying "...is not fully compensated because it is driven by a remote clock pin V9" (which makes sense).

The design works sitting here in my office, but I do get a critical timing warning for the DDR's PLL from TimeQuest (a bunch of setup times are violated) and I was guessing this was caused by the fact that the PLL is being fed from the remote pin but I don't know for sure. I get similar critical timing warnings when I attempt to chain them together too, so perhaps I'm barking up the wrong tree.

Any advice you can give would be greatly appreciated. (I'm a complete newbie with PLLs and global clock resources).

Thanks,

Andrew