Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Neighboring PLLs

I'm using a Cyclone III C25 device (Cyclone III Starter Kit) with Quartus 8.0. Inside my SOPC design I have a NIOS core, a PLL, a DDR controller, and some other peripherals. The clock on ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

The recommendation to use neighboring PLLs when chaining PLL seems to be a new idea of Quartus software designers, not yet found in the Cyclone III handbook. It may have plausible motivations. However, if the design is operating so far, I would ignore the warnings. But there is a recommendation in the handbook to use different PLL bandwidth for source and target PLL.