Hi, I am receiving a negative setup slack time . inst|the_ddr_1|ddr_1_controller_phy_inst|ddr_1_phy_inst|ddr_1_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[1] of -0.706 Can anyone help with me with this and explain the reason of this? Its urgent I have attached the file with failing paths Sneha

The SOPC system is too slow. The path starts at the CPU(Nios) and ends at the DDR2 component, but I have no idea what the SOPC system looks like. There is a section in the SOPC handbook about improving performance that you might want to look at.

HI, But it will definately create a problem when I download the code in the hardware.Is it related to the specifing of the timing constraints? Can you tell which section are you talking about? Sneha

The embedded design handbook has a chapter on Avalon-MM optimizations you can take a look at. It's on the Nios II literature page and probably other places too. Do you have the processor and memory interfaces on different clock domains? I suspect you have asyncronous clock crossing adapters between the CPU and SDRAM which I wouldn't recommend since those adapters only let one access through at a time. You would be better off inserting a clock crossing bridge in between or better yet operate the processor and SDRAM at the same clock frequency. Processors are very sensitive to read latency and by performing any clock crossing between the processor and memory you may hurt the performance rather than improve it. For example if my memory operated up to 150MHz and the CPU could hit say 125MHz it would most likely be best to run them both at 125MHz. This is a generalization and it really depends on the algorithms in the code and cache topology but more often than not this would be the best optimization possible.

Hi, I have used DDR clock timing for all the components in the sopc design to prevent the clock crossing complexity. Do I have to put some timing constraints in the design? I attach the sopc design image

Ok that looks correct. Do you have recovery or removal timing violations in the Timequest report by any chance? Also did you run the .tcl script that is generated by the SDRAM controller? Check to make sure all your I/O are constrained by going into Timequest and running the command "Show all unconstrained I/O".

Negative Setup Slack time | Altera Community

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Altera_Forum
Honored Contributor
14 years ago
That's right. You can cut the output of that node so that timing analysis will not be run on those paths.
Altera_Forum
Honored Contributor
13 years ago
I am also having negative slack issues with the "altera_reserved_tck" signal going through one of the SLD nodes - I dug deep and tracked the signal down to a mega-function core called ALTDDR2 which is being used as part of the design.

Would give some specifics on how to "cut the output of that node" as I don't know the Altera Quartus II interface enough, yet.

Is there a way to constrain that un-constrained signal in the mega-function core or is the only solution is to "cut the output node"?

To be clear, when you "cut the output of that node", does that remove from timing analysis?

The interesting thing about this problem is that the negative slack doesn't start showing up until I have TWO SLD nodes active. If I have a single SLD node, the negative slack is no where to be found. I wonder if this issue has been investigated by Altera to be fixed?

Thanks for you help in advance!!

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Negative Setup Slack time

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