Negative Setup Slack time

Hi,

Yes I do have the time removal violation but I guess that is one of top 20 failing path and I have been able to run the code on the borad with that error of

-2.374 altera_reserved_tck pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|FNUJ6967

But what bothers me is the setup time failure.

I think there is error in clock 1 generator from the pll in the ddr memory.The other clocks dont have any setup time issues.

I am using a ddr2 memory in EP3C120F780C7 with

speed grade of 7

pll reference clk freq 50

memory clock frequency 150

full control data rate with enabled half rate bridge

I really dont understand how to correct it.I have been looking into it for half a month now without any much progress.

Please help its very urgent to me now

I am attaching an word doc of the compilation report for the setup time.

Please give an option to attach excel sheet .It is much easy to post the errors.

I hope it can help find the problem

Sneha