Negative Set Up time in Timing report

I would be surprised if anyone knew exactly(the exact timing models are probably known by internal hardware engineers at Altera.) That being said, I've seen timing numbers represent more than their name. The timing reports very nicely count routing, cell, register delays, but in the silicon it's often not that precise. Tsu is a very idealized term, but it's also racing against the clock, so it might be that the relationship of where the "clock" starts and the "data" starts is throwing it off. If you can get the micro Th of the same path, perhaps it seems out of whack too, but enough that the combination makes sense.