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Altera_Forum
Honored Contributor
16 years agoHi, everybody.
Finally I found my problem. At the end of compilation I read: warning: found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skewinfo: detected ripple clock "generatore_clock:inst|divisore_clock:inst4|clk_out" as buffer Quartus Help suggested me to set constraints for the suspect clock. Once I did it, all went right. Thank you all for your support. See you. Bye bye,;) Alessio. ********************Thread Closed********************