negative edge trigger

Question

hi guys , i need a little help here.

i need to create a negative edge trigger for a period of one clock only.

meaning the signal was at '1' and went down to '0' for one clock period.

does anyone have an idea how to do it in VHDL ?

altera_forum · Answer

to do a negative edge trigger - you flop the signal twice and then AND the second flop with the NOT of the first flop ex:

signal q: std_logic;

signal qq : std_logic;

signal neg_edge_trig : std_logic;

process(clk)

begin

if rising_edge(clk) then

q <= input_signal;

qq <= q;

end if;

end process;

neg_edge_trig <= NOT q AND qq;

altera_forum · Answer

will it preform it for exact one clock period ?? p.s. thank you very much for the replay.

altera_forum · Answer

also wonder , if i want to make it automatically.  should i switch the 'input_signal' by '1' ?

altera_forum · Answer

Yes this will create a 1 cycle pulse following the falling edge of your input signal

altera_forum · Answer

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