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Honored Contributor
Honored ContributorNeed Up To Date Tutorial on Pin Assignments with Schematic Entry
I'm new to Altera Schematic entry tools for their FPGA's. I used Xilinx tools several years ago, but decided to give Altera a try. Anyhow, I downloaded the tutorial "tut_quartus_intro_schem.pdf" wh...
Altera_ForumHonored Contributor
Honored ContributorHi,
you need to compile your design once to have the Pin Planner provide you with a list of your design's signals. I'd forgot to mention this... Regarding your warnings....# 1 and# 2 are informal, i.e. maybe your configurations includes a tick at "parallel compilation" and "logiclock", thus the WebEdition just tells you these features are available only in subscription version. # 3 is as you expected, seems like your target device is not 5V compatible, you'd check in the device's handbook either. The times of FPGAs with 5V I/O pins are generally long time gone. Even the support for 3.3V levels is significantly reduced meanwhile.
