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More easily, create your schematic entry, just run analisys and synthesis and then use the pin planner tool inside QII to give I/O assignment.
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Thanks. Here is what I did.
I clicked PROCESSING-> START-> START ANALYSIS AND SYNTHESIS
Then let it compile for a bit. When done, I clicked ASSIGNMENTS-> PIN PLANNER
My nodes were listed at the bottom of the screen so I just picked the pins I wanted from that. I could also pick the pin I wanted directly and change it to the node.
When that was done, I clicked PROCESSING-> START I/O ASSIGNMENT ANALYSIS
It compiled again, but wasn't happy with my pin selections. I reassigned them, not sure if I did it right, but after a few iterations, the compiler reports 0 errors, 3 warnings.
1. Parallel compilation needs a license.
2. Logiclock needs a license.
3. Pins must meet Altera requirements for 3.3V interfaces and specifically names my two inputs.
I think I can probably ignore warning# 1. Not sure about# 2 because I don't know what logiclock is. Is# 3 just Altera's way of saying the pin is not 5V tolerant?
Anyhow, hopefully this will get me to the next step of the tutorial.
Honored Contributor
