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Altera_Forum
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9 years ago

Need to write timing constraints for PLL generated clocks?

Dear all, I managed to write an SDC file for the external clock with: create_clock -period 40.00 -name {CLK_25MHz} [get_ports {CLK_25MHz}] This clock is the input of a PLL that genera...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

First of all, what does your create_clock constraint look like for the new 48 MHz clock? Is "CLK_48MHz" what you have in the -name argument or is that the name of the clock in your HDL code? Next, if the 48 MHz domain should be separated from all other clock domains, you could simply say:

set_clock_groups -asynchronous -group CLK_48MHz

Having only one -group isolates that clock from all others.