Need advice about coding style

Hello I'm Alex and I am novice for VHDL coding. if my english awful pls forgive me.

I trying to understand VHDL PROCESS statement. I try with 1bit full adder with carry save function in Quartus2 v15.

I write down code:

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
-- truth-table of full-adder
-- with three inputs: ci{carry_in}, a{first in} and b{second in}
-- and two ouputs: s{sum} and co{carry_out}
--  ci a  b | s  co
-- -----------------
--   0 0  0 | 0  0
--   0 0  1 | 1  0
--   0 1  0 | 1  0
--   0 1  1 | 0  1
--   1 0  0 | 1  0
--   1 0  1 | 0  1
--   1 1  0 | 0  1
--   1 1  1 | 1  1
ENTITY full_add_1bit IS
PORT (
    ci : IN STD_LOGIC;
    a : IN  STD_LOGIC;
    b : IN  STD_LOGIC;
    s : OUT STD_LOGIC;
    co : OUT STD_LOGIC
);
END full_add_1bit;
ARCHITECTURE b OF full_add_1bit IS
BEGIN
    p0 : PROCESS(ci, a, b)
    VARIABLE
  aab,
  aob,
  axb,
  sxc : STD_LOGIC;
    BEGIN
  aab := a AND b;
  axb := a XOR b;
  sxc := axb XOR ci;
  s <= sxc;
  IF ci = '0' THEN
   co <= aab;
  ELSIF ci = '1' THEN
   aob := axb XOR aab; -- the same as (a OR b)
   co <= aob;
  END IF;
    END PROCESS p0;
END b;

but during compilation i recieves message

--- Quote Start ---

Warning (10631): VHDL Process Statement warning at full_add_1bit.vhd(30): inferring latch(es) for signal or variable "co", which holds its previous value in one or more paths through the process

--- Quote End ---

I follow the simple logic - let's compute new values then do all signal assignments and the question is

question1 : does pressure on variables so need?!

I rewrite architecture to new one, let's compiler do all work:

ARCHITECTURE b1 OF full_add_1bit IS
BEGIN
    p0 : PROCESS(ci, a, b)
    VARIABLE
  result_i : INTEGER;
    VARIABLE
  result_v : STD_LOGIC_VECTOR (0 TO 1);
    BEGIN
  result_i := CONV_INTEGER(a)+CONV_INTEGER(b)+CONV_INTEGER(ci);
  result_v := CONV_STD_LOGIC_VECTOR (result_i, 2);
  co <= result_v(0);
  s <= result_v(1);
    END PROCESS p0;
END b1;

Finally i make schematic for this with 2mux1 blocks as for fun... in the attachments.

never use schematic for establishing any equation - you waste your time.

But result is the same with that scheme.

question 2: how to find the way to good coding style?