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Altera_Forum
Honored Contributor
Honored ContributorNeed advice about coding style
Hello I'm Alex and I am novice for VHDL coding. if my english awful pls forgive me. I trying to understand VHDL PROCESS statement. I try with 1bit full adder with carry save function in Quartus2 v...
Altera_ForumHonored Contributor
Honored Contributoryes - you get that because you didnt reset all output in the async reset branch.
The prefered style for state machines now is a single clocked process. This avoids any latch creation and can be easier to track. The two process style is a throwback to very old synthesis engines that required separated logic and register processes. And so many textbooks taught this style. Now there is no restriction there is no need to separate logic and registers.
