Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

need a help with strange error" left bound of the range must be a constant "

I have got this problem when I synthesize my design on Quartus II but when I use xilinx software its work perfectly

the error is that " left bound of the range must be a constant "

and it's indicated to this line

-----------------------------------------------

Reg_Q:process (CLK, r_by_2)

begin

if (CLK'event and CLK='1') then

if RESET='1' then

q<= (others => '0');

else

case CS is

-----------------------------------

when S2 =>

q<=p;

-----------------------------------

when S4 =>

if(r_by_2 = 1) then

q <= q (m_size-r_by_2-1 downto 0) & q(m_size-1);

else

---------->>>>> q(m_size-1 downto r_by_2) <= q (m_size - r_by_2 - 1 downto 0);

q(r_by_2-1 downto 0) <= q(m_size-1 downto m_size - r_by_2);

end if;

-----------------------------------

when others =>

null;

-----------------------------------

end case;

end if;

end if;

end process;

-----------------------------------------------

here is the signal definition

signal p, q, t : std_logic_vector (m_size-1 downto 0); --

Does anyone have idea how to make this synthesizable?

Im making a normal basis multiplier

thank you

11 Replies