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Altera_Forum's avatar
Altera_Forum
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18 years ago

multiplying and dividing

I'm trying to use a divider since I don't have the division operator but I'm having some problems. It doesn't seem to like my stage, statements. It says, expression has 4 elements but must have 8 elements. 

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY ADC IS
	PORT (N : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --8 bit signal
		  D : IN STD_LOGIC_VECTOR(5 DOWNTO 0); --6 bit number needed to represent 51
		  ONES : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --4 bit number needed to represent ones digit
		  TENS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); --4 bit number needed to represent tens digit
END ADC;
ARCHITECTURE Structure OF ADC IS
	SIGNAL R: STD_LOGIC_VECTOR(5 DOWNTO 0); --6 bit number to represent remainder
	COMPONENT lpm_divide1
	PORT
	(
		denom		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		numer		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		quotient		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		remain		: OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
	);
    END COMPONENT;
BEGIN
	stage0: lpm_divide1 PORT MAP(D,N,ONES,R);
	stage1: lpm_divide1 PORT MAP(D,R*"1010",TENS,R);
END Structure;

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Maybe you want to declare ONE aend TENS as 8-bit rather than 4-bit to workaround with that? Also, the multiplication R*"1010" may exceed 8 bits. It may causes compilation error. Anyway it seems weird, the R output from both stage0 and stage1. It has the signal congestion. Perhaps it was a mistsake? Hope it helps.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    I made some changes but I'm still getting compiler errors. The error is at stage1: and has to do with R*"1010". This parameter MUST be an 8 bit number for the divider to work. But I guess since R can be as big as 50, x10 = 500, thats bigger than 8 bits so idk what to do 

    LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY ADC IS
	PORT (N : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --8 bit signal
		  --D : IN STD_LOGIC_VECTOR(5 DOWNTO 0); --6 bit number needed to represent 51
		  ONES : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --4 bit number needed to represent ones digit
		  TENS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); --4 bit number needed to represent tens digit
END ADC;
ARCHITECTURE Structure OF ADC IS
	SIGNAL R: STD_LOGIC_VECTOR(5 DOWNTO 0); --6 bit number to represent remainder
	COMPONENT lpm_divide1
	PORT
	(
		denom		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		numer		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		quotient		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		remain		: OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
	);
    END COMPONENT;
BEGIN
	stage0: lpm_divide1 PORT MAP("110011",N,ONES,R);
	stage1: lpm_divide1 PORT MAP("110011",R*"1010",TENS,R);
END Structure;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Why not use the lpm_divide megafunction and then do a BCD on the output?