I made some changes but I'm still getting compiler errors. The error is at stage1: and has to do with R*"1010". This parameter MUST be an 8 bit number for the divider to work. But I guess since R can be as big as 50, x10 = 500, thats bigger than 8 bits so idk what to do
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY ADC IS
PORT (N : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --8 bit signal
--D : IN STD_LOGIC_VECTOR(5 DOWNTO 0); --6 bit number needed to represent 51
ONES : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --4 bit number needed to represent ones digit
TENS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); --4 bit number needed to represent tens digit
END ADC;
ARCHITECTURE Structure OF ADC IS
SIGNAL R: STD_LOGIC_VECTOR(5 DOWNTO 0); --6 bit number to represent remainder
COMPONENT lpm_divide1
PORT
(
denom : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
numer : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
quotient : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
remain : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
stage0: lpm_divide1 PORT MAP("110011",N,ONES,R);
stage1: lpm_divide1 PORT MAP("110011",R*"1010",TENS,R);
END Structure;