Multiplexer testbed simulation/ Quartus II 13.0 64 bit????

Hello there,

I am currently trying to run a testbed simulation of a multiplexer using Quartus II 13.0 64 bit, I followed all the procedures to generate waveforms in conjunction with ModelSim-Altera but there seemed to be a problem with my code. It says: Error (10482): VHDL error at tb_NAME.vhd(83): object "a" is used but not declared

Here is my full code:

Vhdl Test Bench template for design : NAME

--

-- Simulation tool : ModelSim-Altera (VHDL)

--

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY NAME_vhd_tst IS

END NAME_vhd_tst;

ARCHITECTURE NAME_arch OF NAME_vhd_tst IS

-- constants

-- signals

SIGNAL d0 : STD_LOGIC;

SIGNAL d1 : STD_LOGIC;

SIGNAL d2 : STD_LOGIC;

SIGNAL d3 : STD_LOGIC;

SIGNAL f : STD_LOGIC;

SIGNAL s0 : STD_LOGIC;

SIGNAL s1 : STD_LOGIC;

COMPONENT NAME

PORT (

d0 : IN STD_LOGIC;

d1 : IN STD_LOGIC;

d2 : IN STD_LOGIC;

d3 : IN STD_LOGIC;

f : OUT STD_LOGIC;

s0 : IN STD_LOGIC;

s1 : IN STD_LOGIC

);

END COMPONENT;

BEGIN

i1 : NAME

PORT MAP (

-- list connections between master ports and signals

d0 => d0,

d1 => d1,

d2 => d2,

d3 => d3,

f => f,

s0 => s0,

s1 => s1

);

init : PROCESS

-- variable declarations

BEGIN

-- code that executes only once

WAIT;

END PROCESS init;

always : PROCESS

-- optional sensitivity list

-- ( )

-- variable declarations

BEGIN

-- code executes for every event on sensitivity list

a<='0';

b<='0';

wait for 50ns;

a<='1';

b<='0';

wait for 50ns;

a<='0';

b<='1';

wait for 50ns;

a<='1';

b<='1';

wait for 50ns;

a<='0';

b<='0';

wait for 50ns;

WAIT;

END PROCESS always;

BTW, understand I have to declare variable, I'm just not sure how!!!

Tanks in advance

END NAME_arch;