Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Multiple .sdc questions

Hello all! I'm working on gaining a better understanding of using .sdc files, and fully constraining my FPGA (Cyclone III LS) design. I have created clocks and set certain ones exclusive t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Turns out the DMA IP core issue was caused by an interrupt occurring, and then a higher-priority interrupt happening before the first one was completely serviced.

But, if anyone could shed any light on my other questions, it'd make my day!