Forum Discussion
Altera_Forum
Honored Contributor
14 years agoOk, Tricky
I have done just what you suggest in a trivial design: 1) Input.bdf which contains just a input pin and a busline called 'connectToOutput'. 2) Output.bdf which contains just an output pin and a busline called also 'connectToOutput'. 3) symbol file generated for both bdf 4) testFpga.bdf as top, added the two symbols. compiler will say error, no logic in top design 4a) renamed to testFpgaHierarchy.bdf 5) testFpa.bdf which contains both pins and both buslines 'connectToOutput'. compiler will correctely compile! 5a) copy into testFpgaDirect.bdf 6) Archiving the file in testFpga.qar and attached to this post