Forum Discussion
Altera_Forum
Honored Contributor
14 years agoHi Tricky and Cris72
Thank you for info. The basic problem I have, is that the symbols don't get the reference names from the bdf, so the compiler does not connect the names as it does in a single bdf. I would like to have one top-bdf which references the other bdf's in a hierarchical manner and connecting all names automatically, as is done in a single bdf. But that does not work. Currently I am trying to create verilog code from the subbdfs and then to connect them but I have not yet come to a point of success with that approch. I am coming from Object Oriented programming in Smalltalk. There there are very very powerfull concepts for connecting large amounts of names automatically by the great concept of objects. But this seems not to have taken place in hardware design software. Hopefully, I will find a way to use the computer for name referencing also for FPGA design. As stated I am a beginner, I have not done complicated things yet with Quartus...