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Altera_Forum's avatar
Altera_Forum
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13 years ago

Multi source?

Hello. I am trying to make a mac component. Everything is fine, until I put acc (my accumulator) receiving the output value. The strange thing is that Quartus sythetize it, but Modelsim acus...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Try to replace this line 


mac1 : mac GENERIC MAP (size) PORT MAP (clk, rst, a_i, b_i, acc, out_sig);

With this 


mac1 : mac
        GENERIC MAP (
            width => size
            )
        PORT MAP (
            clk     => clk,
            rst     => rst,
            a_i     => a_i,
            b_i     => b_i,
            acc     => acc,
            out_sig => out_sig
            );

If the entity of "mac" has a different signal order then your component declaration you avoid problems with explicitly mapping each signal this way.