Multi source?

Hello.

I am trying to make a mac component. Everything is fine, until I put acc (my accumulator) receiving the output value.

The strange thing is that Quartus sythetize it, but Modelsim acuse a multi-source and responde with X in output value.

Do you guys have any ideas?

Here is the code:

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

ENTITY main IS

generic (

size : integer := 4;

port (

clk : in std_logic;

rst : in std_logic;

a_i : in std_logic_vector(size-1 downto 0);

b_i : in std_logic_vector(size-1 downto 0);

out_o : out std_logic_vector(2*size-1 downto 0)

);

END main;

ARCHITECTURE bhv OF main IS

COMPONENT mac

generic (

width : integer);

port (

clk : in std_logic;

rst : in std_logic;

a_i : in std_logic_vector(width-1 downto 0);

b_i : in std_logic_vector(width-1 downto 0);

acc : in std_logic_vector(2*width-1 downto 0);

out_sig : out std_logic_vector(2*width-1 downto 0)

);

END COMPONENT;

signal acc, out_sig, out_acc : std_logic_vector(2*size-1 downto 0) := (others => '0');

BEGIN

mac1: mac GENERIC MAP (size) PORT MAP (clk, rst, a_i, b_i, acc, out_sig);

reg_out : process(clk, rst)

begin

if rst = '1' then

out_o <= (others => '0');

elsif clk'event and clk = '1' then

out_o <= out_sig;

end if;

end process;

reg_acc : process(clk, rst)

begin

if rst = '1' then

acc <= (others => '0');

elsif clk'event and clk = '1' then

acc <= out_sig;

end if;

end process;

END bhv;