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L982123's avatar
L982123
Icon for New Contributor rankNew Contributor
6 years ago

Multi-phase data recovery design constraints

Hi, I have a design where an input is being oversampled by using multiple phase outputs from a PLL. To make this work I need to ensure that the skew between the input and each sampling register is...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,


We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


Best regards,

KhaiY